Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device

ABSTRACT

A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first contact opening over the exposed active areas; (i) providing an insulating layer over the nitride layer and the polysilicon plug; (j) patterning and etching the insulating layer to form a second contact opening to and exposing the polysilicon plug; and (k) providing a conductive layer over the insulating layer and into the second opening to electrically contact the polysilicon plug. A semiconductor device having buried landing plugs of approximately uniform height across the wafer is also described.

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 5,229,326. The reissue applications are U.S.application Ser. No. 09/488,099 (the present application) and U.S.application Ser. No. 08/504,943, now RE 36,518, of which the presentapplication is a continuation.

TECHNICAL FIELD

This invention relates to semiconductor processing methods for makingelectrical contact with an active area and more particularly, for makingelectrical contact with an active area through sub-micron contactopenings. This invention also relates to semiconductor devices havingburied contact plugs.

BACKGROUND OF THE INVENTION

As semiconductor devices are scaled down to increase packing density,distances between adjacent components are becoming increasingly smaller.Sub-micron geometries are possible with currently availabletechnologies. In some high-density memory devices, distances betweenadjacent word lines are required to be 0.4 micron or less to produce asufficiently dense cell. At these geometries, problems arise whenattempting to define contact openings to active areas between theseadjacent, tightly spaced word lines. Present photolithographic alignmentand metallization techniques are only possible to 0.35 micron features,with a misalignment error of ±0.15 micron. Without the use ofself-aligned active area contacts, the minimum word line spacing wouldbe approximately greater than 0.85 micron which is equal to the minimumphotolithographic feature of 0.35 micron, plus twice the misalignmenttolerance of 0.15 micron, plus twice the processing margin of 0.10micron (or, 0.35 micron+2×0.15 micron+2×0.10 micron=0.85 micron).Present processing techniques are therefore incapable of producingnarrow and properly aligned contact openings to active areas forgeometries of 0.4 micron or less.

This invention provides a processing method for making contacts toactive areas between semiconductor word line (conductive runners) havingsub-micron geometries.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more preferred embodiments of the invention are described belowwith reference to the following accompanying drawings.

FIG. 1 is a diagrammatic section of a semiconductor wafer shown at oneprocessing step in accordance with the invention.

FIG. 2 is a diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 1.

FIG. 3 is a diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 2.

FIG. 4 is a diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 3.

FIG. 5 is a diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 5.

FIG. 6 is a diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 5.

FIG. 7 is a diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 6.

FIG. 8 is a diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 7.

FIG. 9 is diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 8.

FIG. 10 is a diagrammatic section of the FIG. 1 wafer illustrated at aprocessing step subsequent to that shown in FIG. 7. FIG. 10 illustratesadvantages of the present invention in diminishing problems associatedwith misalignment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

In accordance with one aspect of the invention, a semiconductorprocessing method of making electrical contact with an active area on asemiconductor wafer comprises the following steps:

providing a pair of conductive runners on a semiconductor wafer,individual conductive runners having sides;

providing an insulative layer on the sides of the conductive runners,the insulative sides of adjacent conductive runners being spaced aselected distance apart at a selected location on the wafer;

providing an active area between the conductive runners at the selectedlocation;

providing a layer of first oxide to a selected thickness over the activearea and conductive runners, the first oxide layer selected thicknessbeing less than one-half the selected distance between the insulativesides of adjacent conductive runners;

providing a first planarized layer of insulating material atop the firstoxide layer, the first layer of insulating material being selectivelyetchable relative to the first oxide, the first layer of insulatingmaterial having an upper surface;

patterning the planarized first insulating layer for definition of afirst contact opening therethrough to the active area;

etching the patterned first insulating layer selectively relative to thefirst oxide layer to define the first contact opening therethrough, thefirst contact opening having an aperture width at the planarized firstinsulating layer upper surface, the aperture width being greater thanthe selected distance between the insulative sides of adjacentconductive runners;

etching the first oxide layer within the first contact opening to exposethe active area;

providing a plug of conductive material within the first contact openingover the exposed active area;

providing a second insulating layer over the first insulating layer andthe conductive plug;

patterning and etching the second insulating layer to form a secondcontact opening to and exposing the conductive plug; and providing aconductive layer over the second insulating layer and into the secondcontact opening, the conductive layer electrically contacting theconductive plug.

In accordance with another aspect of the invention, the step ofproviding a first planarized layer of insulating material comprises:

providing a conformal first layer of insulating material atop the firstoxide layer; and

chemical mechanical polishing the wafer to planarize the firstinsulating layer.

In accordance with yet another aspect of the invention, a semiconductordevice comprises:

conductive runners formed on the semiconductor wafer, individual runnershaving a top and sides;

insulative spacers provided on the sides of the conductive runners, thespacers of adjacent runners being spaced a selected distance apart atselected locations on the wafer;

active areas positioned between the conductive runners at the selectedlocations;

an insulating layer with an upper surface formed over the runners, theinsulating layer having first contact openings between adjacent runnersabove the selected locations, the first contact openings having anaperture width at the upper surface which is greater than the selecteddistance;

conductive plugs disposed in the first contact openings to electricallycontact the active areas, individual conductive plugs having asubstantially flat upper surface, the upper surfaces of the conductiveplugs being approximately uniform in elevational height across thewafer;

an oxide layer provided above the insulating layer and having secondcontact openings formed therethrough which extend to the upper surfacesof the conductive plugs; and

a conductive layer disposed above the oxide layer and in the secondcontact openings to electrically contact the conductive plugs.

A semiconductor processing method of making electrical contact with anactive area on a semiconductor wafer is described with reference toFIGS. 1-9. The same numbers have been used throughout these figures toreference like parts.

In FIG. 1, a section of a semiconductor wafer 10 has bulk substrate 12,field oxide 14, and active areas 16 and 18. Conductive runners 20, 22,24, and 26 are provided over wafer 10. Individual runners have apolysilicon layer 28, a silicide layer 30, and an oxide layer 32. Gateoxide layers are omitted for purposes of clarity. Individual runners 20,22, 24, and 26 have respective tops 20a, 22a, 24a, and 26a andrespective sides 20b/20c, 22b/22c, 24b/24c, and 26b/26c.

An insulative layer is provided over wafer 10, and then patterned andetched to define insulative spacers 34 on the sides of conductiverunners 20, 22, 24, and 26. Insulative spacers 34 on the sides ofadjacent conductive runners 20, 22 and 24, 26 are spaced a distance Dapart at a selected location on wafer 10 in which a buried contact iseventually formed.

An impurity is implanted into substrate 12 to define source/drainregions 36, 38, 40, and 42. In subsequent steps discussed below, buriedcontact openings are formed to expose source/drain region 38 of activearea 16 and source/drain region 40 of active area 18.

In FIG. 2, a first oxide layer 44 is provided over active areas 16 and18 and conductive runners 20, 22, 24, and 26. First oxide layer 44 has athickness less than one-half of distance D (FIG. 1) between insulativespacers 34 on the sides of adjacent conductive runners 20, 22 and 24,26. First oxide layer 44 is preferably deposited to a thickness fromabout 100 to 1000 Angstroms, with a thickness from about 300 to 500Angstroms being most preferred. First oxide layer 44 has an uppersurface 46 with a contour conforming to the shape of the underlyingsemiconductor components. Upper surface 46 defines a highest elevationallocation K of first oxide layer 44 above active areas 16 and 18.

A thick conformal first layer of insulating material 48 is provided ontop of first oxide layer 44. First insulating layer 48 is formed of amaterial which is selectively etchable relative to first oxide layer 44,and is preferably formed of a nitride. First insulating layer 48 has anupper surface 50 which generally follows the contour defined by theunderlying topography of the runners and field oxide. Upper surface 50defines a lowest elevational location H above active areas 16 and 18which is elevationally higher than highest elevational location K offirst oxide layer 44.

In FIG. 3, semiconductor wafer 10 undergoes chemical mechanicalpolishing (CMP) to planarize first insulating layer 48 and define asubstantially flat upper surface 52. Planarized upper surface 52 is atan elevational location L above active areas 16 and 18 which iselevationally higher than highest elevational location K of first oxidelayer 44. Although the preferred embodiment has been described as atwo-step process involving depositing a conformal insulating layerfollowed by a CMP step to planarize the insulating layer, firstinsulating layer 48 may be deposited in a manner to provide asubstantially planarized upper surface without the need for a subsequentCMP step.

In FIG. 4, first insulating layer 48 is patterned by a mask (not shown)and etched selectively relative to first oxide layer 44 to define firstcontact openings 54 and 56 between adjacent conductive runners 20, 22and 24, 26 above respective source/drain regions 38 and 40 of activeareas 16 and 18. First contact openings 54 and 56 have an aperture widthW at or near upper surface 52 which is greater than distance D betweeninsulative spacers 34 on the sides of adjacent conductive runners 20, 22and 24, 26.

In FIG. 5, first oxide layer 44 is etched within first contact openings54 and 56 to expose respective active areas 16 and 18, or morespecifically, respective source/drain regions 38 and 40 of active areas16 and 18. This etching step is preferably a timed etch, selective tosilicon, which removes the thin oxide layer 44 without detrimentallyetching into insulative spacers 34 or oxide caps 32.

In FIG. 6, plugs 58 and 60 are provided within respective first contactopenings 54 and 56 over the exposed active areas 16 and 18. Plugs 58 and60 are formed of a conductive material and electrically contactsource/drain regions 38 and 40. Preferably, plugs 58 and 60 are formedof polysilicon. Plugs 58 and 60 have respective substantially flat uppersurfaces 62 and 64 which are at an elevational height M above activeareas 16 and 18. Height M is preferably approximately equal to, orslightly lower than, elevational height L of the insulating layer uppersurface 52. Plug surfaces 62 and 64 are approximately uniform inelevational height across the semiconductor wafer. The advantages ofthis globally uniform height are discussed below in more detail.

One of the advantages of this invention is that plugs 58 and 60 haverelatively large upper surface areas. The distance across plugs 58 and60 at upper surfaces 62 and 64 is equal to width W of contact openings54 and 56 (FIG. 4). This distance is significantly greater than distanceD (FIG. 1) of the buried contact region near source/drain regions 34 and40 of substrate 12. Accordingly, the process of this inventioneffectively replaces a narrow contact area near the active area with alarge contact area.

According to one aspect of the invention, conductive plugs 58 and 60 areformed by providing a layer of conductive material (preferablypolysilicon) over first insulating layer 48 and within first contactopenings 54 and 56. The semiconductor wafer is then subjected tochemical mechanical polishing to remove the conductive layer from uppersurface 52 of first insulating layer 48. All the conductive material isremoved from upper surface 52 to electrically isolate individual plugs58 and 60 and to prevent formation of undesired stray conductive tracesbetween conductive plugs 58 and 60. To help insure that all conductivematerial is removed from upper surface 52, plugs 58 and 60 are overpolished such that plug surfaces 62 ad 64 are slightly below firstinsulating layer upper surface 52. In this manner, individual plugs 58and 60 are electrically isolated from one another.

An alternative technique to chemical mechanical polishing is to subjectthe layer of conductive material to a resist etch back process to definethe slightly recessed plug surfaces 62 and 64 of respective plugs 58 and60.

In FIG. 7, a second insulating layer 66 is provided over firstinsulating layer 48 and plugs 58 and 60. Second insulating layer 66 maybe an oxide layer such as BPSG.

In FIG. 8, second insulating layer 66 is patterned beneath a mask (notshown) and etched to form second contact openings 68 and 70 which exposerespective upper surfaces 62 and 64 of conductive plugs 58 and 60.Second insulating layer 66 is preferably dry etched with an etchantselective to both insulating layer 48 (which is preferably a nitridelayer) and polysilicon plugs 58 and 60 (which are preferablypolysilicon). Due to the relatively large surface areas of plugs 58 and60 and the etch selectivity, conventional photolithographic techniquesmay be used to form second contact openings 68 and 70. First insulatinglayer 48 and oxide layer 44 assist in protecting conductive runners 20,22, 24, and 26 during this etching step. The etchant may removeinsulating layer 48 at a different rate than polysilicon plugs 58 and 60as illustrated by surface level discontinuities 71 at the interfacebetween insulating layer 48 and plugs 58 and 60.

In FIG. 9, a conductive layer 76 is provided over second insulatinglayer 66 and into second contact openings 68 and 70 to electricallycontact plugs 58 and 60. Conductive layer 76 may be formed bypolysilicon or metal.

Another advantage provided by this invention relates to misalignmenttolerance. In FIG. 10, second insulating layer 66 is undesirablypatterned and etched to form misaligned contact openings 72 an 74.Despite this misalignment, however, electrical contact with active areas16 and 18 is still achieved through respective plugs 58 and 60 due tothe large surface area at upper plug surfaces 62 and 64 (in comparisonto the narrow distance D of the buried contact opening between adjacentrunners near active areas 16 and 18). Additionally, etching secondcontact layer 66 with an etchant selective to both first insulatinglayer 48 and conductive plugs 58 and 60 permits significant misalignmentwhile still protecting the underlying structure. The present inventiontherefore provides desirable misalignment tolerance which results inhigher yields of processed semiconductor devices.

This invention defines a processing method for submicron geometries, andis most useful at geometries of less than 0.4 micron. The combined thinoxide and thick nitride layers afford a structure suitable for highlyselective etching to define contact openings on the scale of 0.3 to 0.4micron. The uniformly elevated and significantly wide landing plugsprovide an easy target for conventional photolithographic techniqueswhen forming the second contact openings. Additionally, the wide landingplugs provide misalignment tolerance which helps increase productionyield.

In compliance with the statute, the invention has been described inlanguage more or less specific as to methodical features. It is to beunderstood, however, that the invention is not limited to the specificfeatures described, since the means herein disclosed comprise preferredforms of putting the invention into effect. The invention is, therefore,claimed in any of its forms or modifications within the proper scope ofthe appended claims appropriately interpreted in accordance with thedoctrine of equivalents.

1. A semiconductor processing method of making electrical contact withan active area on a semiconductor wafer, the method comprising thefollowing steps: providing a pair of conductive runners on asemiconductor wafer, individual conductive runners having sides;providing an insulative layer on the sides of the conductive runners,the insulative sides of adjacent conductive runners being spaced aselected distance apart at a selected location on the wafer; providingan active area between the conductive runners at the selected location;providing a layer of first oxide to a selected thickness over the activearea and conductive runners, the first oxide layer selected thicknessbeing less than one-half the selected distance between the insulativesides of adjacent conductive runners; providing a first planarized layerof insulating material atop the first oxide layer, the first layer ofinsulating material being selectively etchable relative to the firstoxide, the first layer of insulating material having an upper surface;patterning the planarized first insulating layer for definition of afirst contact opening therethrough to the active area; etching thepatterned first insulating layer selectively relative to the first oxidelayer to define the first contact opening therethrough, the firstcontact opening having an aperture width at the planarized firstinsulating layer upper surface, the aperture width being greater thanthe selected distance between the insulative sides of adjacentconductive runners; etching the first oxide layer within the firstcontact opening to expose the active area; providing a plug ofconductive material within the first contact opening over the exposedactive area; providing a second insulating layer over the firstinsulating layer and the conductive plug; patterning and etching thesecond insulating layer to form a second contact opening to and exposingthe conductive plug; and providing a conductive layer over the secondinsulating layer and into the second contact opening, the conductivelayer electrically contacting the conductive plug.
 2. A semiconductorprocessing method according to claim 1 wherein the selected first oxidelayer thickness is from about 100 to 1,000 Angstroms.
 3. A semiconductorprocessing method according to claim 1 wherein the selected first oxidelayer thickness is from about 300 to 500 Angstroms.
 4. A semiconductorprocessing method according to claim 1 wherein the first insulatinglayer is formed of a nitride.
 5. A semiconductor processing methodaccording to claim 1 wherein the conductive plug is formed ofpolysilicon.
 6. A semiconductor processing method according to claim 1wherein the step of providing a first planarized layer of insulatingmaterial comprises: providing a conformal first layer of insulatingmaterial atop the first oxide layer; and chemical mechanical polishingthe wafer to planarize the first insulating layer.
 7. A semiconductorprocessing method according to claim 1 wherein the first insulatinglayer has an upper surface and wherein the step of providing a plug ofconductive material comprises: providing a layer of conductive materialover the first insulating layer and within the first contact openingover the exposed active area; chemical mechanical polishing the wafer toremove the conductive layer from the first insulating layer uppersurface and to define a plug within the first contact opening, the plughaving an upper surface slightly below the first insulating layer uppersurface to ensure that the plug is electrically isolated.
 8. Asemiconductor processing method according to claim 1 wherein the secondinsulating layer is etched with an etchant selective to both the firstinsulating layer and the conductive plug.
 9. A semiconductor processingmethod according to claim 1 wherein: the first insulating layer isformed of a nitride; the conductive plug is formed of polysilicon; andthe second insulating layer is etched with an etchant selective to boththe nitride insulating layer and the polysilicon plug.
 10. Asemiconductor processing method for making electrical contact with anactive area on a semiconductor wafer comprising the steps of: providinga pair of conductive runners on a semiconductor wafer, individualconductive runners having a top and sides; providing insulative spacerson the sides of the runners, the insulative spacers being spaced aselected distance apart at a selected location on the wafer; providingan active area between the conductive runners at the selected location;depositing a first oxide layer over the wafer to a thickness from about100 to 1,000 Angstroms, the first oxide layer having an upper surfacedefining a highest elevational location above the active area; providinga nitride layer having an upper surface over the first oxide layer to aselected thickness, the nitride layer upper surface defining a lowestelevational location above the active area which is elevationally higherthan the highest elevational location of the first oxide layer, thenitride being selectively etchable relative to the first oxide;planarizing the nitride layer to a first elevational height above theactive area, the first elevational height being higher than the highestelevational location of the first oxide layer; patterning the planarizednitride layer for definition of a first contact opening therethrough tothe active area; etching the patterned nitride layer selectivelyrelative to the first oxide layer to define the first contact openingtherethrough, the first contact opening having an aperture width at thenitride layer upper surface which is greater than the selected distancebetween the insulative sides of adjacent conductive runners; etching thefirst oxide layer within the first contact opening to expose the activearea; providing a polysilicon plug within the first contact opening overthe exposed active area to a second elevational height; depositing asecond oxide layer over the nitride layer and the polysilicon plug;patterning and etching the second oxide layer to form a second contactopening to and exposing the polysilicon plug; and providing a conductivelayer over the second oxide layer and into the second contact opening,the conductive layer electrically contacting the conductive plug.
 11. Asemiconductor processing method according to claim 10 wherein theselected first oxide layer thickness is from about 300 to 500 Angstroms.12. A semiconductor processing method according to claim 10 wherein thestep of planarizing the nitride layer comprises chemical mechanicalpolishing the wafer to planarize the nitride layer.
 13. A semiconductorprocessing method according to claim 10 wherein the step of providing apolysilicon plug comprises: providing a layer of polysilicon over thenitride layer and within the first contact opening over the exposedactive area; chemical mechanical polishing the wafer to remove thepolysilicon layer from the nitride layer upper surface and to define apolysilicon plug within the first contact opening.
 14. A semiconductorprocessing method according to claim 10 wherein the second oxide layeris etched by an etchant selective to both the nitride layer and thepolysilicon plug.
 15. A semiconductor processing method according toclaim 10 wherein the second elevational height is approximately equal tothe first elevational height.
 16. A semiconductor processing methodaccording to claim 10 wherein the second elevational height is slightlylower than the first elevational height.
 17. A semiconductor processingmethod of forming an electrical contact structure for an active area ona semiconductor wafer, the method comprising the following steps:providing a pair of conductive runners on a semiconductor wafer,individual conductive runners having sides; providing an insulativelayer on the mutually adjacent sides of the conductive runners, theinsulated mutually adjacent sides of adjacent conductive runners beingspaced a selected distance apart; providing an active area between theinsulated mutually adjacent sides of conductive runners; providing alayer of first oxide to a selected thickness over the active area andconductive runners, the first oxide layer selected thickness being lessthan one-half the selected distance between the insulated sides ofadjacent conductive runners; providing a first insulating layer having aplanarized upper surface atop the first oxide layer, the first layer ofinsulating material being selectively etchable relative to the firstoxide; patterning the first insulating layer for definition of a firstcontact opening therethrough to the active area; etching the patternedfirst insulating layer selectively relative to the first oxide layer todefine the first contact opening therethrough, the first contact openinghaving an aperture width at the first insulating layer planarized uppersurface, the aperture width being greater than the selected distancebetween the insulated sides of adjacent conductive runners; etching thefirst oxide layer within the first contact opening to expose the activearea; and providing a conductive plug of within the first contactopening over the exposed active area.
 18. A semiconductor processingmethod according to claim 17 wherein the step of providing a plug ofconductive material comprises: providing a layer of conductive materialover the first insulating layer and within the first contact openingover the exposed active area; and polishing the wafer to remove theconductive layer from the first insulating layer planarized uppersurface and to define the conductive plug within the first contactopening, the plug having an upper surface slightly below the firstinsulating layer planarized upper surface.
 19. A semiconductorprocessing method according to claim 17 further comprising: providing asecond insulating layer and the conductive plug; and patterning andetching the second insulating layer to form a second contact opening toexpose the conductive plug.
 20. A semiconductor processing methodaccording to claim 19 further comprising etching the second insulatinglayer with an etchant selective to both the first insulating layer andthe conductive plug.
 21. A semiconductor processing method according toclaim 19 further comprising: forming the first insulating layer of anitride; forming the conductive plug of polysilicon; and etching thesecond insulating layer with an etchant selective to both the nitrideinsulating layer and the polysilicon plug.
 22. A semiconductorprocessing method of forming an electrical contact structure for anactive area on a semiconductor wafer, the method comprising thefollowing steps: providing a pair of conductive runners on asemiconductor wafer, individual conductive runners having sides;providing an insulative layer on the mutually adjacent sides of theconductive runners, the insulated mutually adjacent sides of adjacentconductive runners being spaced a selected distance apart; providing anactive area between the insulated mutually adjacent sides of conductiverunners; providing a layer of first oxide to a selected thickness overthe active area and conductive runners, the first oxide layer selectedthickness being less than one-half the selected distance between theinsulated sides of adjacent conductive runners; providing a firstinsulating layer having a planarized upper surface atop the first oxidelayer, the first insulating layer being selectively etchable relative tothe first oxide, said step performed by, providing a conformal firstlayer of insulating material atop the first oxide layers; and polishingthe wafer to planarize the first insulating layer upper surface;patterning the first insulating layer for definition of a first contactopening therethrough to the active area; etching the patterned firstinsulating layer selectively relative to the first oxide layer to definethe first contact opening therethrough, the first contact opening havingan aperture width at the first insulating layer planarized uppersurface, the aperture width being greater than the selected distancebetween the insulated sides of adjacent conductive runners; etching thefirst oxide layer within the first contact opening to expose the activearea; and providing a conductive plug within the first contact openingover the exposed active area.
 23. A semiconductor processing method formaking electrical contact with an active area on a semiconductor wafercomprising the steps of: providing a pair of conductive runners on asemiconductor wafer, individual conductive runners having a top andsides; providing insulative spacers on mutually adjacent sides of therunners, the insulative spacers being spaced a selected distance apartat a selected location on the wafer; providing an active area betweenthe conductive runners at the selected location; depositing a firstoxide layer over the wafer to a thickness from about 100 to 1,000Angstroms, the first oxide layer having an upper surface defining ahighest elevational location above the active area; providing a nitridelayer having an upper surface over the first oxide layer to a selectedthickness, the nitride layer upper surface defining a lowest elevationallocation above the active area which is elevationally higher than thehighest elevational location of the first oxide layer, the nitride beingselectively etchable relative to the first oxide; planarizing an uppersurface of the nitride layer to a first elevational height above theactive area, the first elevational height being higher than the highestelevational location of the first oxide layer upper surface; patterningthe nitride layer for definition of a first contact opening therethroughto the active area; etching the patterned nitride layer selectivelyrelative to the first oxide layer to define the first contact openingtherethrough, the first contact opening having an aperture width at thenitride layer upper surface which is greater than the selected distancebetween the insulative spacers at the mutually adjacent sides of theconductive runners; etching the first oxide layer within the firstcontact opening to expose the active area; providing a polysilicon plugwithin the first contact opening over the exposed active area to asecond elevational height; and depositing a second oxide layer over thenitride layer and the polysilicon plug.
 24. A semiconductor processingmethod according to claim 23 wherein the step of planarizing the nitridelayer comprises polishing the wafer to planarize the nitride layer. 25.A semiconductor processing method according to claim 23 wherein the stepof providing a polysilicon plug comprises: providing a layer ofpolysilicon over the nitride layer and within the first contact openingover the exposed active area; and polishing the wafer to remove thepolysilicon layer from the nitride layer upper surface and to define apolysilicon plug within the first contact opening.
 26. A semiconductorprocessing method according to claim 23 further comprising etching thesecond oxide layer by an etchant selective to both the nitride layer andthe polysilicon plug.
 27. A method of providing electrical communicationwith a transistor including a source/drain, said method comprising:providing a conductor over said source/drain that extends upward and islaterally surrounded by a first layer of insulation; providing a secondlayer of insulation over said first layer of insulation, wherein saidsecond layer of insulation is higher than said conductor and exposessaid conductor; and allowing electrical communication with saidsource/drain only by way of said conductor.
 28. The method in claim 27,wherein said step of providing a conductor comprises providing a plug.29. A method of processing a device comprising a transistor, said methodcomprising: providing a plug in electrical communication with saidtransistor; providing a conductive material in electrical communicationwith said plug; and providing an insulating layer lateral to saidconductive material, wherein said step of providing an insulating layeroccurs before said step of providing a conductive material.
 30. Themethod in claim 29, further comprising a step of providing a firstinsulating layer over said transistor; and wherein said step ofproviding an insulating layer lateral to said conductive materialcomprises providing a second insulating layer over said first insulatinglayer.
 31. The method in claim 30, wherein said step of providing aconductive material is discrete from said step of providing a plug.